-------------------------------------------------------------------------------
--
-- Title       : No Title
-- Design      : test1
-- Author      : aldec
-- Company     : Microsoft
--
-------------------------------------------------------------------------------
--
-- File        : C:\Users\vincenti\Desktop\testworkspace\wkspace\compile\test1.vhd
-- Generated   : 02/10/15 11:07:54
-- From        : C:\Users\vincenti\Desktop\testworkspace\wkspace\src\test1.asf
-- By          : FSM2VHDL ver. 5.0.7.2
--
-------------------------------------------------------------------------------
--
-- Description : 
--
-------------------------------------------------------------------------------

library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.std_logic_arith.all;
use IEEE.std_logic_unsigned.all;

entity test1 is 
	port (
		a: in STD_LOGIC;
		clk: in STD_LOGIC;
		enable: in STD_LOGIC;
		reset: in STD_LOGIC;
		z: out STD_LOGIC);
end test1;

architecture test1_arch of test1 is

-- diagram signals declarations
signal delay_counter_Sreg0: INTEGER range 0 to 3;

-- SYMBOLIC ENCODED state machine: Sreg0
type Sreg0_type is (
    S1, S2, S3, S4_S5, S4_D1_DS1
);
-- attribute ENUM_ENCODING of Sreg0_type: type is ... -- enum_encoding attribute is not supported for symbolic encoding

signal Sreg0: Sreg0_type;

begin


----------------------------------------------------------------------
-- Machine: Sreg0
----------------------------------------------------------------------
Sreg0_machine: process (clk)
begin
	if rising_edge(clk) then
		if reset='1' then
			Sreg0 <= S1;
			-- Set default values for outputs, signals and variables
			-- ...
			z <= '0';
		else
			if enable = '1' then
				-- Set default values for outputs, signals and variables
				-- ...
				if Sreg0 = S1 then
					z <= '0';
					if a='1' then
						Sreg0 <= S2;
					end if;
				elsif Sreg0 = S2 then
					z <= '1';
					if a='1' then
						Sreg0 <= S4_S5;
					end if;
				elsif Sreg0 = S3 then
					z <= '0';
					if a='1' then
						Sreg0 <= S1;
					end if;
				elsif Sreg0 = S4_S5 then
					Sreg0 <= S4_D1_DS1;
					delay_counter_Sreg0 <= 3 - 1;
				elsif Sreg0 = S4_D1_DS1 then
					if delay_counter_Sreg0 = 0 then
						Sreg0 <= S3;
					else
						Sreg0 <= S4_D1_DS1;
						if delay_counter_Sreg0 /= 0 then delay_counter_Sreg0 <= delay_counter_Sreg0 - 1;
						end if;
					end if;
--vhdl_cover_off
				else
					null;
--vhdl_cover_on
				end if;
			end if;
		end if;
	end if;
end process;

end test1_arch;
